Summary of IEDM 2020 Conference

December 2020

This is my summary of the IEDM conference held virtually in December 2020. This summary focuses on papers and presentations around embedded memory IP and system aspects that are ready for mass market use. However, the conference featured several sessions with research articles on new memory concepts and approaches, like Ferroelectric Memories and ideas for In-memory computing. As always, I encourage you to procure the articles and study these in detail.

Tutorial 6: STT and SOT MRAM Technologies and their Applications from IoT to AI Systems.

The conference kicked off with a series of Tutorials made available from Saturday December 5th. Most interesting from an embedded memory perspective was the tutorial from Dr. Tetsuo Endoh from Tohoku University in Japan on “STT and SOT MRAM Technologies and Its Applications from IoT to AI System”. The tutorial starts by walking through the different MRAM solutions for various memory classes, including some of the recently published work included in my magnetic immunity study.

Then the fundamental challenge of MRAM is presented as the tradeoff between write current, endurance, and thermal stability, which sets the retention and magnetic immunity properties of the MTJ. Dr. Endoh highlights that the optimum for this challenge must be found in the process integration of MTJ.

To try to optimize this tradeoff, Dr. Endoh introduces a new MTJ stack, the Quad MTJ (QMTJ), which builds on the Dual MTJ (DMTJ) introduced earlier and has an additional free layer in the stack. The QMTJ is especially interesting from an embedded Flash perspective, as it shows roughly 2x thermal stability performance compared to the DMTJ at the same dimensions. This directly correlates to higher retention and magnetic immunity. In addition, the QMTJ also shows improved performance wrt. write power, write speed and endurance.

I had the opportunity to ask Dr. Endoh a couple of questions about the QMTJ during the live session. Most interestingly Dr. Endoh said that, given the two free layers in the stack, a metastable state could be theoretically possible, but this would only be caused by a bad design. A metastable state has not been observed in their work so far, but looking at the switching curves, it is hardly distinguishable due to the fast switching (< 1ns). Still, this is a possibility which needs to be considered and analyzed in a practical implementation, and with respect to possible back-hopping effects.

In his tutorial Dr. Endoh also covered the state of SOT-MRAM as well as NV logic with CMOS/MTJ hybrid technologies. I strongly encourage you to watch this session.

Short Course 2: Memory Bound Computing

In this short course, a series of speakers discussed options and scenarios for various memory bound computing solutions. Due to my background in security solutions, I found the two sessions on security especially interesting. They were on ”Memory for Secure Computing” by Prof. Todd Austin from University of Michigan and “PUFs for Hardware Security” by Dr. Sanu Mathew from Intel.

Prof. Austin gave a good insight into the various memory vulnerabilities or bugs that can occur in secure systems, and explained the key concepts around symmetric and asymmetric encryption, side-channel attacking as well as secure boot and secure execution. A key point from Prof. Austin in the live session was that security vulnerabilities in hardware often occur in the regions when the hardware is about to fail. This means that extra care should be taken by the system architects to implement countermeasures and protect the system when the temperature is high or the power supply is low. I would add two points to this. Firstly, for embedded IP, the design kit provided by most IP vendors is usually not geared to handle operation in these areas accurately. IP vendors tend to characterize their IP to show how well it works and spend little effort investigating regions at the boundary of operation, where it may fail. If security is a concern for your system, you should discuss with your IP vendor the accuracy of the design kit in these critical conditions or regions. Secondly, for new emerging memory types there may be new vulnerabilities, which may impact the system security scenarios. An example of this is magnetic immunity for MRAM, which is covered in MRAM Magnetic Immunity – An Empirical Study. Prof. Austin's was a very well-presented short course and a good introduction for those not familiar with the topic.

Dr. Mathew continued the security topic with a great walkthrough of various PUF categories and architectures as well as metrics for evaluating the PUF functionality. The PUF, or Physically Unclonable Function, is a key element for providing a device-unique identifier for use in e.g. encryption algorithms. Dr. Mathews showed some of the well-known PUF architectures based on SRAM cells and new RRAM based implementations. He also explained some of the methods to remove random variations in the PUF values to achieve a stable result. Finally, Dr. Mathew presented two strong PUF implementations that can withstand Machine learning attacks by reducing predictability to 50% even with several million learning cycles and a 128b challenge. If you are looking at adding or implementing PUF functionality in your system, I highly recommend this presentation as an introduction to the subject.

Session 6: Memory Technology - Charge Based

Most of the papers in this session were focused on 3D NAND SCM or DRAM implementations. However, one paper sounded very interesting, as it was on ”Vertical Split-Gate Flash Memory for Embedded Flash Scaling” by Tzu-Hsuan Hsu, Macronix, Taiwan. Unfortunately, after a closer look, this paper had several issues. Although it was trying to show a mature memory technology, it was more a concept study.

The paper presents a vertical split gate memory cell as promised and tries to argue that this is a replacement for embedded NOR Flash below the 2x node. It further tries to show that this memory can be used for implementing Compute-in-Memory (CIM) MAC operations with several bits per cell resolution.

Firstly, I am struggling to understand how this can be classified as an embedded memory, since the author shows this memory integrated on a separate die above a logic and SRAM die with Cu hybrid bonding. Secondly, the reliability plots shown are poor, with 0.5V retention drift in cell Vt within the first 60s. I tried to ask the author if this was not a relaxation mechanism after cycling, rather than true retention charge loss, and his comments were that they needed more work on the retention study to understand this drift. Looking at the cell IV curves, such a drift would cover the whole current range intended for the multi-bit cell, hence taking the retention/relaxation effect into account would void the CIM use-case.

The other memory reliability metrics look promising and are comparable to NOR Flash, however it should not be considered a true embedded memory.

Session 11: Memory Technology - STT-MRAM Technology

This was by far the most interesting session from an embedded memory standpoint.

The session was started by Thomas Jew (TJ) from NXP, with whom I have worked closely in the NXP NVM management team. TJ showed in his invited paper how MRAM can be easily adopted as Flash replacement into existing MCU systems, and SRAM replacement in MPU systems, which typically have external Flash. TJ stated that MRAM is basically ready for wide deployment, which will in most cases lead to simplifications in the memory management system compared to Flash. In addition, he explained how MRAM can create new opportunities for system performance and power reduction compared to Flash based systems.

TJ also commented on the magnetic immunity problem, and, especially in the live session, somewhat downplayed the importance of this effect in real life. He is, of course, correct that if the memory is kept centimeters away from strong magnets, and your memory can handle > 200 Oe, there should be no problem with current offerings. However, especially for MRAM targeting SRAM replacement, the magnetic immunity can be much lower. Everspin Technologies e.g. specifies a max magnetic immunity of 25 Oe for their products. As TJ mentioned, there are several options for dealing with magnetic fields, such as active detection and recovery, and passive shielding, but many of these are still in the research state. If you are interested in learning more about magnetic immunity, please check out my study of MRAM offerings and real-life use-cases mentioned earlier.

The second paper from Samsung focused on MRAM implementation for frame buffer applications. The frame buffer application requires faster writes and higher endurance, but trades this off with retention which is only a few minutes at 85degC. The paper shows three different MRAM implementations using the same MTJ technology, one targeting Flash replacement with solder reflow capability, one for Flash replacement without solder reflow, and one for the MRAM for Frame buffer with higher write speed and lower retention. The author commented in the live session that the difference in the MTJ stack dimensions is roughly 20% between the three implementations. This is another example of how MRAM reliability and performance properties can be traded off through MTJ CD dimensions and operating voltages/timings.

The third paper was from GlobalFoundries, and gave an update on their embedded MRAM development, as reported in the above magnetic immunity study. Dr. Nail presented the latest status of the 22nm FDSOI MRAM offering, showing very impressive reliability metrics (ECC off). Additionally, he showed active immunity of up to 500 Oe, and some examples of improved MRAM magnetic immunity by adding different layers of magnetic shielding. Unfortunately, the specifics on the shields are not yet disclosed. Finally, he showed the module failure rate vs. ECC level similar to the graph included in the MI study mentioned earlier. Luckily his numbers match mine.

The last paper I report on here is the fourth paper in this session presented by Yi-Chun Shih from TSMC on their 8Mb STT-MRAM solution in 16nm with solder reflow capability. TSMC has further scaled the MRAM cell down to 0.033um2 in the 16nm node (from 0.0456um2 in 22nm) and they showed that biasing has been significantly simplified compared to the 22nm implementation. Thus, the negative voltage on the unselected WL and the inhibit voltage on BL and CSL are no longer needed. Finally, they showed a merged reference scheme using several MTJ’s in parallel and antiparallel state to generate the reference current. As the references see significantly more active current, they have biased each of the MTJ’s such that the current passes the cell in the enforcing direction, thereby eliminating read disturb on the read references. One concern that I brought up in the live session was that MTJ’s in the merged reference could fail or get corrupted. This would lead to massive read failure. According to the author, the system can tolerate single MTJ failures due to the averaging, so there is no plan to reinforce or rewrite the reference cells. This could however be an option and is likely possible as the reference level is already trimmable.

Session 24: Memory Technology - Emerging Memory (PCRAM/RRAM/MRAM)

In this session I will focus on two articles, one on PCM and one on RRAM. Other articles in this session focused mainly on research for bringing these memories to advanced nodes below 10nm.

The PCM article was presented by Franck Arnaud from ST Microelectronics, and shows impressive progress on the PCM memory for Automotive applications earlier presented at 2019 Symposium on VLSI Circuits. The article presents a 16MB PCM memory IP fully performing to Automotive grade-0 reliability in 28FDSOI with the smallest reported eNVM cell size of 0.019um2. The memory has solder reflow capability and has a reading window of 5uA (@1ppm) at 165degC even after 250K cycles. The performance and cell size have been achieved with some advanced processing, which does mean increased mask count. The cell uses a special Super-STI (SSTI), which creates the needed isolation without introducing defects and dislocations in the lattice, and a super compact BJT selector. At the live session I asked the author about the mask count, and he mentioned that the BJT requires and additional 2 masks, and the SSTI needs no additional mask. This is on top of the mask count for adding the PCM element. The Author further commented that it will be possible to shrink the cell size further going to 1xnm nodes, as the cell size is still set by the selector device.

The RRAM paper presents a 14nm Oxide based RRAM memory by Xiaoxin Xu from IMECAS in China. One of the problems bringing RRAM to lower nodes is that the forming of the filament in the RRAM requires high voltages, which can exceed the breakdown capability of the transistors at smaller nodes. To avoid this problem, the paper introduces a deep NWell for the select transistor, which enables the voltages across the select transistor to stay within the breakdown limits by having a negative bulk, and distributes the BL, WL and SL voltages around 0V. Further, the paper introduces an optimized programming scheme with dual voltage levels, which results in a more uniform distribution of LRS and HRS states as well as better reliability. Finally, the paper analyzes the effect of programming current with respect to retention metrics for this RRAM implementation. The conclusion is that at least 100uA program current is needed per bit to achieve acceptable BER for production. Note however that an acceptable BER target in this paper looks to be around 2000ppm after 1000hrs bake at 150degC, and even after 1hr bake the BER reaches 1000ppm. The paper offers some interesting ideas that could be applied to production-ready RRAM memories at 14nm and below, like the dual voltage program scheme and negative bulk selector. However, there are some unanswered questions around reliability and power consumption of this solution.

IEDM 2020 Conclusion

IEDM was a very interesting conference with a huge number of relevant topics and excellent papers. It has in the past been recognized as one of the key conferences for new memory updates, and it did not disappoint this year.

In addition to the memory papers summarized here, the conference had several other sessions on memory technology topics, like ferroelectric memory, in-memory computing and 3D memories, as well as many other interesting semiconductor device topics covered in the total 41 sessions held. I highly recommend that you gain access to the papers and presentations and explore some of the many other topics discussed in other tracks.

Compared to last years IEDM conference there were however limited news on embedded STT-MRAM for Flash replacement or new improvements on magnetic immunity. Only GlobalFoundries and TSMC presenting slight updates to their offerings in this area. STT-MRAM looks to be moving from a research topic to production, which may explain the limited news on this front.

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